// *********************************************************************************
// Project Name : zkx2024
// Author       : Glqu
// Email        : QGL_MAX@163.com
// Create Time  : 2024-05-02
// File Name    : wr_sram_ctrl.v
// Module Name  : wr_sram_ctrl
// Called By    :
// Abstract     :
//
// 
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2024-05-02    Macro           1.0                     Original
//  
// *********************************************************************************
module wr_sram_ctrl(
    input WR_EN_0,
    input [12:0] WR_ADDR_0,
    input [35:0] WR_DATA_0,
    input [4:0] WR_SRAM_NUM_0,
    input WR_EN_1,
    input [12:0] WR_ADDR_1,
    input [35:0] WR_DATA_1,
    input [4:0] WR_SRAM_NUM_1,
    input WR_EN_2,
    input [12:0] WR_ADDR_2,
    input [35:0] WR_DATA_2,
    input [4:0] WR_SRAM_NUM_2,
    input WR_EN_3,
    input [12:0] WR_ADDR_3,
    input [35:0] WR_DATA_3,
    input [4:0] WR_SRAM_NUM_3,
    input WR_EN_4,
    input [12:0] WR_ADDR_4,
    input [35:0] WR_DATA_4,
    input [4:0] WR_SRAM_NUM_4,
    input WR_EN_5,
    input [12:0] WR_ADDR_5,
    input [35:0] WR_DATA_5,
    input [4:0] WR_SRAM_NUM_5,
    input WR_EN_6,
    input [12:0] WR_ADDR_6,
    input [35:0] WR_DATA_6,
    input [4:0] WR_SRAM_NUM_6,
    input WR_EN_7,
    input [12:0] WR_ADDR_7,
    input [35:0] WR_DATA_7,
    input [4:0] WR_SRAM_NUM_7,
    input WR_EN_8,
    input [12:0] WR_ADDR_8,
    input [35:0] WR_DATA_8,
    input [4:0] WR_SRAM_NUM_8,
    input WR_EN_9,
    input [12:0] WR_ADDR_9,
    input [35:0] WR_DATA_9,
    input [4:0] WR_SRAM_NUM_9,
    input WR_EN_10,
    input [12:0] WR_ADDR_10,
    input [35:0] WR_DATA_10,
    input [4:0] WR_SRAM_NUM_10,
    input WR_EN_11,
    input [12:0] WR_ADDR_11,
    input [35:0] WR_DATA_11,
    input [4:0] WR_SRAM_NUM_11,
    input WR_EN_12,
    input [12:0] WR_ADDR_12,
    input [35:0] WR_DATA_12,
    input [4:0] WR_SRAM_NUM_12,
    input WR_EN_13,
    input [12:0] WR_ADDR_13,
    input [35:0] WR_DATA_13,
    input [4:0] WR_SRAM_NUM_13,
    input WR_EN_14,
    input [12:0] WR_ADDR_14,
    input [35:0] WR_DATA_14,
    input [4:0] WR_SRAM_NUM_14,
    input WR_EN_15,
    input [12:0] WR_ADDR_15,
    input [35:0] WR_DATA_15,
    input [4:0] WR_SRAM_NUM_15,
    input WR_EN_16,
    input [12:0] WR_ADDR_16,
    input [35:0] WR_DATA_16,
    input [4:0] WR_SRAM_NUM_16,
    input WR_EN_17,
    input [12:0] WR_ADDR_17,
    input [35:0] WR_DATA_17,
    input [4:0] WR_SRAM_NUM_17,
    input WR_EN_18,
    input [12:0] WR_ADDR_18,
    input [35:0] WR_DATA_18,
    input [4:0] WR_SRAM_NUM_18,
    input WR_EN_19,
    input [12:0] WR_ADDR_19,
    input [35:0] WR_DATA_19,
    input [4:0] WR_SRAM_NUM_19,
    input WR_EN_20,
    input [12:0] WR_ADDR_20,
    input [35:0] WR_DATA_20,
    input [4:0] WR_SRAM_NUM_20,
    input WR_EN_21,
    input [12:0] WR_ADDR_21,
    input [35:0] WR_DATA_21,
    input [4:0] WR_SRAM_NUM_21,
    input WR_EN_22,
    input [12:0] WR_ADDR_22,
    input [35:0] WR_DATA_22,
    input [4:0] WR_SRAM_NUM_22,
    input WR_EN_23,
    input [12:0] WR_ADDR_23,
    input [35:0] WR_DATA_23,
    input [4:0] WR_SRAM_NUM_23,
    input WR_EN_24,
    input [12:0] WR_ADDR_24,
    input [35:0] WR_DATA_24,
    input [4:0] WR_SRAM_NUM_24,
    input WR_EN_25,
    input [12:0] WR_ADDR_25,
    input [35:0] WR_DATA_25,
    input [4:0] WR_SRAM_NUM_25,
    input WR_EN_26,
    input [12:0] WR_ADDR_26,
    input [35:0] WR_DATA_26,
    input [4:0] WR_SRAM_NUM_26,
    input WR_EN_27,
    input [12:0] WR_ADDR_27,
    input [35:0] WR_DATA_27,
    input [4:0] WR_SRAM_NUM_27,
    input WR_EN_28,
    input [12:0] WR_ADDR_28,
    input [35:0] WR_DATA_28,
    input [4:0] WR_SRAM_NUM_28,
    input WR_EN_29,
    input [12:0] WR_ADDR_29,
    input [35:0] WR_DATA_29,
    input [4:0] WR_SRAM_NUM_29,
    input WR_EN_30,
    input [12:0] WR_ADDR_30,
    input [35:0] WR_DATA_30,
    input [4:0] WR_SRAM_NUM_30,
    input WR_EN_31,
    input [12:0] WR_ADDR_31,
    input [35:0] WR_DATA_31,
    input [4:0] WR_SRAM_NUM_31,
    input WR_EN_32,
    input [12:0] WR_ADDR_32,
    input [35:0] WR_DATA_32,
    input [4:0] WR_SRAM_NUM_32,
    input WR_EN_33,
    input [12:0] WR_ADDR_33,
    input [35:0] WR_DATA_33,
    input [4:0] WR_SRAM_NUM_33,
    input WR_EN_34,
    input [12:0] WR_ADDR_34,
    input [35:0] WR_DATA_34,
    input [4:0] WR_SRAM_NUM_34,
    input WR_EN_35,
    input [12:0] WR_ADDR_35,
    input [35:0] WR_DATA_35,
    input [4:0] WR_SRAM_NUM_35,
    input WR_EN_36,
    input [12:0] WR_ADDR_36,
    input [35:0] WR_DATA_36,
    input [4:0] WR_SRAM_NUM_36,
    input WR_EN_37,
    input [12:0] WR_ADDR_37,
    input [35:0] WR_DATA_37,
    input [4:0] WR_SRAM_NUM_37,
    input WR_EN_38,
    input [12:0] WR_ADDR_38,
    input [35:0] WR_DATA_38,
    input [4:0] WR_SRAM_NUM_38,
    input WR_EN_39,
    input [12:0] WR_ADDR_39,
    input [35:0] WR_DATA_39,
    input [4:0] WR_SRAM_NUM_39,
    input WR_EN_40,
    input [12:0] WR_ADDR_40,
    input [35:0] WR_DATA_40,
    input [4:0] WR_SRAM_NUM_40,
    input WR_EN_41,
    input [12:0] WR_ADDR_41,
    input [35:0] WR_DATA_41,
    input [4:0] WR_SRAM_NUM_41,
    input WR_EN_42,
    input [12:0] WR_ADDR_42,
    input [35:0] WR_DATA_42,
    input [4:0] WR_SRAM_NUM_42,
    input WR_EN_43,
    input [12:0] WR_ADDR_43,
    input [35:0] WR_DATA_43,
    input [4:0] WR_SRAM_NUM_43,
    input WR_EN_44,
    input [12:0] WR_ADDR_44,
    input [35:0] WR_DATA_44,
    input [4:0] WR_SRAM_NUM_44,
    input WR_EN_45,
    input [12:0] WR_ADDR_45,
    input [35:0] WR_DATA_45,
    input [4:0] WR_SRAM_NUM_45,
    input WR_EN_46,
    input [12:0] WR_ADDR_46,
    input [35:0] WR_DATA_46,
    input [4:0] WR_SRAM_NUM_46,
    input WR_EN_47,
    input [12:0] WR_ADDR_47,
    input [35:0] WR_DATA_47,
    input [4:0] WR_SRAM_NUM_47,

    output reg [35:0] W_DATA,
    output reg [12:0] W_ADDR,
    output reg WR
);

parameter WR_SRAM_num=5'd0;

assign WR=  (WR_SRAM_NUM_0==WR_SRAM_num)&&WR_EN_0 ||
            (WR_SRAM_NUM_1==WR_SRAM_num)&&WR_EN_1 ||
            (WR_SRAM_NUM_2==WR_SRAM_num)&&WR_EN_2 ||
            (WR_SRAM_NUM_3==WR_SRAM_num)&&WR_EN_3 ||
            (WR_SRAM_NUM_4==WR_SRAM_num)&&WR_EN_4 ||
            (WR_SRAM_NUM_5==WR_SRAM_num)&&WR_EN_5 ||
            (WR_SRAM_NUM_6==WR_SRAM_num)&&WR_EN_6 ||
            (WR_SRAM_NUM_7==WR_SRAM_num)&&WR_EN_7 ||
            (WR_SRAM_NUM_8==WR_SRAM_num)&&WR_EN_8 ||
            (WR_SRAM_NUM_9==WR_SRAM_num)&&WR_EN_9 ||
            (WR_SRAM_NUM_10==WR_SRAM_num)&&WR_EN_10 ||
            (WR_SRAM_NUM_11==WR_SRAM_num)&&WR_EN_11 ||
            (WR_SRAM_NUM_12==WR_SRAM_num)&&WR_EN_12 ||
            (WR_SRAM_NUM_13==WR_SRAM_num)&&WR_EN_13 ||
            (WR_SRAM_NUM_14==WR_SRAM_num)&&WR_EN_14 ||
            (WR_SRAM_NUM_15==WR_SRAM_num)&&WR_EN_15 ||
            (WR_SRAM_NUM_16==WR_SRAM_num)&&WR_EN_16 ||
            (WR_SRAM_NUM_17==WR_SRAM_num)&&WR_EN_17 ||
            (WR_SRAM_NUM_18==WR_SRAM_num)&&WR_EN_18 ||
            (WR_SRAM_NUM_19==WR_SRAM_num)&&WR_EN_19 ||
            (WR_SRAM_NUM_20==WR_SRAM_num)&&WR_EN_20 ||
            (WR_SRAM_NUM_21==WR_SRAM_num)&&WR_EN_21 ||
            (WR_SRAM_NUM_22==WR_SRAM_num)&&WR_EN_22 ||
            (WR_SRAM_NUM_23==WR_SRAM_num)&&WR_EN_23 ||
            (WR_SRAM_NUM_24==WR_SRAM_num)&&WR_EN_24 ||
            (WR_SRAM_NUM_25==WR_SRAM_num)&&WR_EN_25 ||
            (WR_SRAM_NUM_26==WR_SRAM_num)&&WR_EN_26 ||
            (WR_SRAM_NUM_27==WR_SRAM_num)&&WR_EN_27 ||
            (WR_SRAM_NUM_28==WR_SRAM_num)&&WR_EN_28 ||
            (WR_SRAM_NUM_29==WR_SRAM_num)&&WR_EN_29 ||
            (WR_SRAM_NUM_30==WR_SRAM_num)&&WR_EN_30 ||
            (WR_SRAM_NUM_31==WR_SRAM_num)&&WR_EN_31 ||
            (WR_SRAM_NUM_32==WR_SRAM_num)&&WR_EN_32 ||
            (WR_SRAM_NUM_33==WR_SRAM_num)&&WR_EN_33 ||
            (WR_SRAM_NUM_34==WR_SRAM_num)&&WR_EN_34 ||
            (WR_SRAM_NUM_35==WR_SRAM_num)&&WR_EN_35 ||
            (WR_SRAM_NUM_36==WR_SRAM_num)&&WR_EN_36 ||
            (WR_SRAM_NUM_37==WR_SRAM_num)&&WR_EN_37 ||
            (WR_SRAM_NUM_38==WR_SRAM_num)&&WR_EN_38 ||
            (WR_SRAM_NUM_39==WR_SRAM_num)&&WR_EN_39 ||
            (WR_SRAM_NUM_40==WR_SRAM_num)&&WR_EN_40 ||
            (WR_SRAM_NUM_41==WR_SRAM_num)&&WR_EN_41 ||
            (WR_SRAM_NUM_42==WR_SRAM_num)&&WR_EN_42 ||
            (WR_SRAM_NUM_43==WR_SRAM_num)&&WR_EN_43 ||
            (WR_SRAM_NUM_44==WR_SRAM_num)&&WR_EN_44 ||
            (WR_SRAM_NUM_45==WR_SRAM_num)&&WR_EN_45 ||
            (WR_SRAM_NUM_46==WR_SRAM_num)&&WR_EN_46 ||
            (WR_SRAM_NUM_47==WR_SRAM_num)&&WR_EN_47;

assign W_DATA=  ({36{((WR_SRAM_NUM_0==WR_SRAM_num)&&WR_EN_0)}}&WR_DATA_0)|
                ({36{((WR_SRAM_NUM_1==WR_SRAM_num)&&WR_EN_1)}}&WR_DATA_1)|
                ({36{((WR_SRAM_NUM_2==WR_SRAM_num)&&WR_EN_2)}}&WR_DATA_2)|
                ({36{((WR_SRAM_NUM_3==WR_SRAM_num)&&WR_EN_3)}}&WR_DATA_3)|
                ({36{((WR_SRAM_NUM_4==WR_SRAM_num)&&WR_EN_4)}}&WR_DATA_4)|
                ({36{((WR_SRAM_NUM_5==WR_SRAM_num)&&WR_EN_5)}}&WR_DATA_5)|
                ({36{((WR_SRAM_NUM_6==WR_SRAM_num)&&WR_EN_6)}}&WR_DATA_6)|
                ({36{((WR_SRAM_NUM_7==WR_SRAM_num)&&WR_EN_7)}}&WR_DATA_7)|
                ({36{((WR_SRAM_NUM_8==WR_SRAM_num)&&WR_EN_8)}}&WR_DATA_8)|
                ({36{((WR_SRAM_NUM_9==WR_SRAM_num)&&WR_EN_9)}}&WR_DATA_9)|
                ({36{((WR_SRAM_NUM_10==WR_SRAM_num)&&WR_EN_10)}}&WR_DATA_10)|
                ({36{((WR_SRAM_NUM_11==WR_SRAM_num)&&WR_EN_11)}}&WR_DATA_11)|
                ({36{((WR_SRAM_NUM_12==WR_SRAM_num)&&WR_EN_12)}}&WR_DATA_12)|
                ({36{((WR_SRAM_NUM_13==WR_SRAM_num)&&WR_EN_13)}}&WR_DATA_13)|
                ({36{((WR_SRAM_NUM_14==WR_SRAM_num)&&WR_EN_14)}}&WR_DATA_14)|
                ({36{((WR_SRAM_NUM_15==WR_SRAM_num)&&WR_EN_15)}}&WR_DATA_15)|
                ({36{((WR_SRAM_NUM_16==WR_SRAM_num)&&WR_EN_16)}}&WR_DATA_16)|
                ({36{((WR_SRAM_NUM_17==WR_SRAM_num)&&WR_EN_17)}}&WR_DATA_17)|
                ({36{((WR_SRAM_NUM_18==WR_SRAM_num)&&WR_EN_18)}}&WR_DATA_18)|
                ({36{((WR_SRAM_NUM_19==WR_SRAM_num)&&WR_EN_19)}}&WR_DATA_19)|
                ({36{((WR_SRAM_NUM_20==WR_SRAM_num)&&WR_EN_20)}}&WR_DATA_20)|
                ({36{((WR_SRAM_NUM_21==WR_SRAM_num)&&WR_EN_21)}}&WR_DATA_21)|
                ({36{((WR_SRAM_NUM_22==WR_SRAM_num)&&WR_EN_22)}}&WR_DATA_22)|
                ({36{((WR_SRAM_NUM_23==WR_SRAM_num)&&WR_EN_23)}}&WR_DATA_23)|
                ({36{((WR_SRAM_NUM_24==WR_SRAM_num)&&WR_EN_24)}}&WR_DATA_24)|
                ({36{((WR_SRAM_NUM_25==WR_SRAM_num)&&WR_EN_25)}}&WR_DATA_25)|
                ({36{((WR_SRAM_NUM_26==WR_SRAM_num)&&WR_EN_26)}}&WR_DATA_26)|
                ({36{((WR_SRAM_NUM_27==WR_SRAM_num)&&WR_EN_27)}}&WR_DATA_27)|
                ({36{((WR_SRAM_NUM_28==WR_SRAM_num)&&WR_EN_28)}}&WR_DATA_28)|
                ({36{((WR_SRAM_NUM_29==WR_SRAM_num)&&WR_EN_29)}}&WR_DATA_29)|
                ({36{((WR_SRAM_NUM_30==WR_SRAM_num)&&WR_EN_30)}}&WR_DATA_30)|
                ({36{((WR_SRAM_NUM_31==WR_SRAM_num)&&WR_EN_31)}}&WR_DATA_31)|
                ({36{((WR_SRAM_NUM_32==WR_SRAM_num)&&WR_EN_32)}}&WR_DATA_32)|
                ({36{((WR_SRAM_NUM_33==WR_SRAM_num)&&WR_EN_33)}}&WR_DATA_33)|
                ({36{((WR_SRAM_NUM_34==WR_SRAM_num)&&WR_EN_34)}}&WR_DATA_34)|
                ({36{((WR_SRAM_NUM_35==WR_SRAM_num)&&WR_EN_35)}}&WR_DATA_35)|
                ({36{((WR_SRAM_NUM_36==WR_SRAM_num)&&WR_EN_36)}}&WR_DATA_36)|
                ({36{((WR_SRAM_NUM_37==WR_SRAM_num)&&WR_EN_37)}}&WR_DATA_37)|
                ({36{((WR_SRAM_NUM_38==WR_SRAM_num)&&WR_EN_38)}}&WR_DATA_38)|
                ({36{((WR_SRAM_NUM_39==WR_SRAM_num)&&WR_EN_39)}}&WR_DATA_39)|
                ({36{((WR_SRAM_NUM_40==WR_SRAM_num)&&WR_EN_40)}}&WR_DATA_40)|
                ({36{((WR_SRAM_NUM_41==WR_SRAM_num)&&WR_EN_41)}}&WR_DATA_41)|
                ({36{((WR_SRAM_NUM_42==WR_SRAM_num)&&WR_EN_42)}}&WR_DATA_42)|
                ({36{((WR_SRAM_NUM_43==WR_SRAM_num)&&WR_EN_43)}}&WR_DATA_43)|
                ({36{((WR_SRAM_NUM_44==WR_SRAM_num)&&WR_EN_44)}}&WR_DATA_44)|
                ({36{((WR_SRAM_NUM_45==WR_SRAM_num)&&WR_EN_45)}}&WR_DATA_45)|
                ({36{((WR_SRAM_NUM_46==WR_SRAM_num)&&WR_EN_46)}}&WR_DATA_46)|
                ({36{((WR_SRAM_NUM_47==WR_SRAM_num)&&WR_EN_47)}}&WR_DATA_47);

assign W_ADDR=  ({13{((WR_SRAM_NUM_0==WR_SRAM_num)&&WR_EN_0)}}&WR_ADDR_0)|
                ({13{((WR_SRAM_NUM_1==WR_SRAM_num)&&WR_EN_1)}}&WR_ADDR_1)|
                ({13{((WR_SRAM_NUM_2==WR_SRAM_num)&&WR_EN_2)}}&WR_ADDR_2)|
                ({13{((WR_SRAM_NUM_3==WR_SRAM_num)&&WR_EN_3)}}&WR_ADDR_3)|
                ({13{((WR_SRAM_NUM_4==WR_SRAM_num)&&WR_EN_4)}}&WR_ADDR_4)|
                ({13{((WR_SRAM_NUM_5==WR_SRAM_num)&&WR_EN_5)}}&WR_ADDR_5)|
                ({13{((WR_SRAM_NUM_6==WR_SRAM_num)&&WR_EN_6)}}&WR_ADDR_6)|
                ({13{((WR_SRAM_NUM_7==WR_SRAM_num)&&WR_EN_7)}}&WR_ADDR_7)|
                ({13{((WR_SRAM_NUM_8==WR_SRAM_num)&&WR_EN_8)}}&WR_ADDR_8)|
                ({13{((WR_SRAM_NUM_9==WR_SRAM_num)&&WR_EN_9)}}&WR_ADDR_9)|
                ({13{((WR_SRAM_NUM_10==WR_SRAM_num)&&WR_EN_10)}}&WR_ADDR_10)|
                ({13{((WR_SRAM_NUM_11==WR_SRAM_num)&&WR_EN_11)}}&WR_ADDR_11)|
                ({13{((WR_SRAM_NUM_12==WR_SRAM_num)&&WR_EN_12)}}&WR_ADDR_12)|
                ({13{((WR_SRAM_NUM_13==WR_SRAM_num)&&WR_EN_13)}}&WR_ADDR_13)|
                ({13{((WR_SRAM_NUM_14==WR_SRAM_num)&&WR_EN_14)}}&WR_ADDR_14)|
                ({13{((WR_SRAM_NUM_15==WR_SRAM_num)&&WR_EN_15)}}&WR_ADDR_15)|
                ({13{((WR_SRAM_NUM_16==WR_SRAM_num)&&WR_EN_16)}}&WR_ADDR_16)|
                ({13{((WR_SRAM_NUM_17==WR_SRAM_num)&&WR_EN_17)}}&WR_ADDR_17)|
                ({13{((WR_SRAM_NUM_18==WR_SRAM_num)&&WR_EN_18)}}&WR_ADDR_18)|
                ({13{((WR_SRAM_NUM_19==WR_SRAM_num)&&WR_EN_19)}}&WR_ADDR_19)|
                ({13{((WR_SRAM_NUM_20==WR_SRAM_num)&&WR_EN_20)}}&WR_ADDR_20)|
                ({13{((WR_SRAM_NUM_21==WR_SRAM_num)&&WR_EN_21)}}&WR_ADDR_21)|
                ({13{((WR_SRAM_NUM_22==WR_SRAM_num)&&WR_EN_22)}}&WR_ADDR_22)|
                ({13{((WR_SRAM_NUM_23==WR_SRAM_num)&&WR_EN_23)}}&WR_ADDR_23)|
                ({13{((WR_SRAM_NUM_24==WR_SRAM_num)&&WR_EN_24)}}&WR_ADDR_24)|
                ({13{((WR_SRAM_NUM_25==WR_SRAM_num)&&WR_EN_25)}}&WR_ADDR_25)|
                ({13{((WR_SRAM_NUM_26==WR_SRAM_num)&&WR_EN_26)}}&WR_ADDR_26)|
                ({13{((WR_SRAM_NUM_27==WR_SRAM_num)&&WR_EN_27)}}&WR_ADDR_27)|
                ({13{((WR_SRAM_NUM_28==WR_SRAM_num)&&WR_EN_28)}}&WR_ADDR_28)|
                ({13{((WR_SRAM_NUM_29==WR_SRAM_num)&&WR_EN_29)}}&WR_ADDR_29)|
                ({13{((WR_SRAM_NUM_30==WR_SRAM_num)&&WR_EN_30)}}&WR_ADDR_30)|
                ({13{((WR_SRAM_NUM_31==WR_SRAM_num)&&WR_EN_31)}}&WR_ADDR_31)|
                ({13{((WR_SRAM_NUM_32==WR_SRAM_num)&&WR_EN_32)}}&WR_ADDR_32)|
                ({13{((WR_SRAM_NUM_33==WR_SRAM_num)&&WR_EN_33)}}&WR_ADDR_33)|
                ({13{((WR_SRAM_NUM_34==WR_SRAM_num)&&WR_EN_34)}}&WR_ADDR_34)|
                ({13{((WR_SRAM_NUM_35==WR_SRAM_num)&&WR_EN_35)}}&WR_ADDR_35)|
                ({13{((WR_SRAM_NUM_13==WR_SRAM_num)&&WR_EN_13)}}&WR_ADDR_36)|
                ({13{((WR_SRAM_NUM_37==WR_SRAM_num)&&WR_EN_37)}}&WR_ADDR_37)|
                ({13{((WR_SRAM_NUM_38==WR_SRAM_num)&&WR_EN_38)}}&WR_ADDR_38)|
                ({13{((WR_SRAM_NUM_39==WR_SRAM_num)&&WR_EN_39)}}&WR_ADDR_39)|
                ({13{((WR_SRAM_NUM_40==WR_SRAM_num)&&WR_EN_40)}}&WR_ADDR_40)|
                ({13{((WR_SRAM_NUM_41==WR_SRAM_num)&&WR_EN_41)}}&WR_ADDR_41)|
                ({13{((WR_SRAM_NUM_42==WR_SRAM_num)&&WR_EN_42)}}&WR_ADDR_42)|
                ({13{((WR_SRAM_NUM_43==WR_SRAM_num)&&WR_EN_43)}}&WR_ADDR_43)|
                ({13{((WR_SRAM_NUM_44==WR_SRAM_num)&&WR_EN_44)}}&WR_ADDR_44)|
                ({13{((WR_SRAM_NUM_45==WR_SRAM_num)&&WR_EN_45)}}&WR_ADDR_45)|
                ({13{((WR_SRAM_NUM_46==WR_SRAM_num)&&WR_EN_46)}}&WR_ADDR_46)|
                ({13{((WR_SRAM_NUM_47==WR_SRAM_num)&&WR_EN_47)}}&WR_ADDR_47);

endmodule

